Combinational equivalence checking using satisfiability and recursive learning
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Least Upper Bounds for the Size of OBDDs Using Symmetry Properties
IEEE Transactions on Computers
Automatic test bench generation for validation of RT-level descriptions: an industrial experience
DATE '00 Proceedings of the conference on Design, automation and test in Europe
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A proof engine approach to solving combinational design automation problems
Proceedings of the 39th annual Design Automation Conference
Induction-based gate-level verification of multipliers
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Applied Boolean Equivalence Verification and RTL Static Sign-Off
IEEE Design & Test
Optimizing Multiple EDA Tools within the ASIC Design Flow
IEEE Design & Test
Automatic Validation of Protocol Interfaces Described in VHDL
Real-World Applications of Evolutionary Computing, EvoWorkshops 2000: EvoIASP, EvoSCONDI, EvoTel, EvoSTIM, EvoROB, and EvoFlight
Branching vs. Linear Time: Final Showdown
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Static Property Checking Using ATPG v.s. BDD Techniques
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set
IEEE Transactions on Computers
Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Debugging sequential circuits using Boolean satisfiability
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Post-verification debugging of hierarchical designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 43rd annual Design Automation Conference
Automated Fault Localization for C Programs
Electronic Notes in Theoretical Computer Science (ENTCS)
Abstraction and refinement techniques in automated design debugging
Proceedings of the conference on Design, automation and test in Europe
Pragmatic equivalence and safety checking in Cryptol
Proceedings of the 3rd workshop on Programming languages meets program verification
A succinct memory model for automated design debugging
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
The day Sherlock Holmes decided to do EDA
Proceedings of the 46th Annual Design Automation Conference
A formal approach for debugging arithmetic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On formal equivalence verification of hardware
CSR'08 Proceedings of the 3rd international conference on Computer science: theory and applications
Solving satisfiability in combinational circuits with backtrack search and recursive learning
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Managing verification error traces with bounded model debugging
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
From RTL to silicon: the case for automated debug
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Managing complexity in design debugging with sequential abstraction and refinement
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Boosting minimal unsatisfiable core extraction
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Debugging with dominance: on-the-fly RTL debug solution implications
Proceedings of the International Conference on Computer-Aided Design
Formal verification of backward compatibility of microcode
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Path directed abstraction and refinement in SAT-based design debugging
Proceedings of the 49th Annual Design Automation Conference
A safety-focused verification using software fault trees
Future Generation Computer Systems
Towards efficient MUS extraction
AI Communications - 18th RCRA International Workshop on “Experimental evaluation of algorithms for solving problems with combinatorial explosion”
EPR-based bounded model checking at word level
IJCAR'12 Proceedings of the 6th international joint conference on Automated Reasoning
Implicative simultaneous satisfiability and applications
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
Non-solution implications using reverse domination in a modern SAT-based debugging environment
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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