Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Software testing techniques (2nd ed.)
Software testing techniques (2nd ed.)
Sequential logic testing and verification
Sequential logic testing and verification
An observability-based code coverage metric for functional simulation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
From Design Validation to Hardware Testing: A Unified Approach
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Formal Equivalence Checking and Design DeBugging
Formal Equivalence Checking and Design DeBugging
Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms
EvoIASP '99/EuroEcTel '99 Proceedings of the First European Workshops on Evolutionary Image Analysis, Signal Processing and Telecommunications
Testability Analysis and ATPG on Behavioral RT-Level VHDL
Proceedings of the IEEE International Test Conference
Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
VEGA: A Verification Tool Based on Genetic Algorithms
ICCD '98 Proceedings of the International Conference on Computer Design
ARPIA: A High-Level Evolutionary Test Signal Generator
Proceedings of the EvoWorkshops on Applications of Evolutionary Computing
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In present days, most of the design activity is performed at a high level of abstraction, thus designers need to be sure that their designs are syntactically and semantically correct before starting the automatic synthesis process. The goal of this paper is to propose an automatic input pattern generation tool able to assist designers in the generation of a test bench for difficult parts of small-or medium-sized digital protocol interfaces. The proposed approach exploit a Genetic Algorithm connected to a commercial simulator for cultivating a set of input sequence able to execute given statements in the interface description. The proposed approach has been evaluated on the new ITC'99 benchmark set, a collection of circuits offering a wide spectrum of complexity. Experimental results show that some portions of the circuits remained uncovered, and the subsequent manual analysis allowed identifying design redundancies.