On behavior fault modeling for digital designs
Journal of Electronic Testing: Theory and Applications
Constraint-Based Automatic Test Data Generation
IEEE Transactions on Software Engineering
IEEE Design & Test
From Specification Validation to Hardware Testing: A Unified Method
Proceedings of the IEEE International Test Conference on Test and Design Validity
B-algorithm: A Behavioral-Test Generation Algorithm
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
High-level test generation using physically-induced faults
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Automatic test bench generation for simulation-based validation
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Automatic test bench generation for validation of RT-level descriptions: an industrial experience
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Automatic Validation of Protocol Interfaces Described in VHDL
Real-World Applications of Evolutionary Computing, EvoWorkshops 2000: EvoIASP, EvoSCONDI, EvoTel, EvoSTIM, EvoROB, and EvoFlight
System-Level Test Bench Generation in a Co-Design Framework
ETW '00 Proceedings of the IEEE European Test Workshop
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments
Journal of Electronic Testing: Theory and Applications
Mutation Sampling Technique for the Generation of Structural Test Data
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Using model-based test program generator for simulation validation
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
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In this paper we propose a new approach that addresses boththe problems of design validation and hardware testing since theearly stages of the design flow. The approach consists in adaptingthe mutation testing, a software method, to circuits described inVHDL. At the functional level, the approach behaves as a designvalidation method and at the hardware level as a classical ATPG.Standard software test metrics are used for assessing the quality ofthe design validation process, and the hardware fault coverage forassessing the test quality at the hardware level. An enhancementprocess that allows design validation to be efficiently reused forhardware testing is detailed. The approach is shown to be efficientupon a set of representative circuits.