Functional fault modeling and simulation for VLSI devices
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A heuristic chip-level test generation algorithm
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Introduction to Switching Theory and Logical Design
Introduction to Switching Theory and Logical Design
GSP: A logic simulator for LSI
DAC '81 Proceedings of the 18th Design Automation Conference
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Simulation techniques for microprocessors
DAC '77 Proceedings of the 14th Design Automation Conference
Micro-operation perturbations in chip level fault modeling
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
From Design Validation to Hardware Testing: A Unified Approach
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Microprocessor Architecture Design with ATLAS
IEEE Design & Test
On-line testing of scalable signal processing architectures using a software test method
ITC '98 Proceedings of the 1998 IEEE International Test Conference
ACM SIGDA Newsletter
B-algorithm: a behavioral test generation algorithm
ITC'94 Proceedings of the 1994 international conference on Test
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VLSI circuits have made gate-level modeling of large-scale systems impractical. Chip-level modeling offers an alternative approach to model development that still represents timing accurately. The authors examine this approach to modeling and the use of hardware description languages (HDLs) to achieve the desired accuracy. The characteristics of chip-level models are reviewed and sample models are presented. HDL code for each model is given to illustrate its use. Fault modeling in a chip level is examined.