Design verification and performance analysis
DAC '78 Proceedings of the 15th Design Automation Conference
SCALD: Structured Computer-Aided Logic Design
DAC '78 Proceedings of the 15th Design Automation Conference
The SCALD physical design subsystem
DAC '78 Proceedings of the 15th Design Automation Conference
Electrical considerations in the computer aided design of logic circuit interconnections
DAC '73 Proceedings of the 10th Design Automation Workshop
An accurate time delay model for large digital network simulation
DAC '76 Proceedings of the 13th Design Automation Conference
TEGAS2—anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic
DAC '72 Proceedings of the 9th Design Automation Workshop
Race analysis of digital systems without logic simulation
DAC '71 Proceedings of the 8th Design Automation Workshop
Design validation in hierarchical systems
DAC '75 Proceedings of the 12th Design Automation Conference
Design verification of large scientific computers
DAC '77 Proceedings of the 14th Design Automation Conference
An hierarchical language for the structural description of digital systems
DAC '77 Proceedings of the 14th Design Automation Conference
Statistical failure analysis of system timing
IBM Journal of Research and Development
Delay optimization of combinational static CMOS logic
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Timing verification and the timing analysis program
25 years of DAC Papers on Twenty-five years of electronic design automation
Formal Verification of Fault Tolerance Using Theorem-Proving Techniques
IEEE Transactions on Computers
On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing analysis in a logic synthesis environment
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing verification using HDTV
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Simulation of digital circuits in the presence of uncertainty
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Algorithms for timing requirement analysis and generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Timing analysis in high-level synthesis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Functional timing analysis for IP characterization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ACTAS: an accurate timing analysis system for VLSI
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A unified approach to simulation and timing verification at the functional level
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Development of a timing analysis program for multiple clocked network
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
SCAT—a new statistical timing verifier in a silicon compiler system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An accuration delay modeling technique for switch-level timing verification
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Plug-in timing models for an abstract timing verifier
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Testing and Debugging Custom Integrated Circuits
ACM Computing Surveys (CSUR)
17th design automation conference report June 23-25, 1980
ACM SIGDA Newsletter
IEEE Design & Test
Statistical techniques of timing verification
DAC '83 Proceedings of the 20th Design Automation Conference
Path delay analysis for hierarchical building block layout system
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
A timing verification system based on extracted MOS/VLSI circuit parameters
DAC '81 Proceedings of the 18th Design Automation Conference
Custom VLSI electrical rule checking in an intelligent terminal
DAC '81 Proceedings of the 18th Design Automation Conference
Developments in verification of design correctness (A Tutorial)
DAC '80 Proceedings of the 17th Design Automation Conference
Speed and accuracy in digital network simulation based on structural modeling
DAC '82 Proceedings of the 19th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Timing verification system based on delay time hierarchical nature
DAC '82 Proceedings of the 19th Design Automation Conference
Synchronous path analysis in MOS circuit simulator
DAC '82 Proceedings of the 19th Design Automation Conference
VLSI tools and architectures: Putting the new technology to work
CSC-83 Proceedings of the 1983 computer science conference
Formal verification of timing conditions
EURO-DAC '90 Proceedings of the conference on European design automation
TATOO: an industrial timing analyzer with false path elimination and test pattern generation
EURO-DAC '91 Proceedings of the conference on European design automation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing analysis of computer hardware
IBM Journal of Research and Development
Static timing analysis for flexible TFT circuits
Proceedings of the 47th Design Automation Conference
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A new approach to the verification of the timing constraints on large digital systems has been developed. The associated algorithm is computationally very efficient, and provides early and continuous feedback about the timing aspects of synchronous sequential circuits as they are designed. It also provides means for conveniently verifying the design in sections, permitting the section-by-section timing verification of designs which are too large to examine as a unit on existing computer systems. A system using this algorithm has been implemented, and has been used to verify the timing constraints on the design of the S-1 Mark IIA processor.