A graph-theoretic approach for timing analysis and its implementation
IEEE Transactions on Computers - Special Issue on Real-Time Systems
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Timing verification using HDTV
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Timing distribution in VHDL behavioral models
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
EDTC '96 Proceedings of the 1996 European conference on Design and Test
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Timing requirement analysis removes ambiguity from specifications and generates results for use in other simulations of digital systems. It involves construction of a graph representing all constraints between state transitions and the generation of an optimized graph having a maximum number of simultaneous constraints. Optimization involves prioritizing the constraints or searching for a solution which violates no constraints.