An Approach for a Dynamic Generation/Validation System for the Functional Simulation Considering Timing Constraints

Authors:
Ulrich Heinkel;Wolfram H. Glauert
Affiliations:
University of Erlangen-Nuremberg, Institute for Computer-Aided Circuit Design, Cauerstrasse 6,91058 Erlangen;University of Erlangen-Nuremberg, Institute for Computer-Aided Circuit Design, Cauerstrasse 6,91058 Erlangen
Venue:
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Year:
1996

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Abstract

This paper presents a method for the automatic validation of the timing behavior of RT and gate level VHDL descriptions. Using a machine-readable timing specification, we automatically create a VHDL testbench for the stimuli generation and the validation of the expected responses. We have developed a VHDL package using linear programming algorithms to compute a valid set of stimuli. The model responses are checked dynamically subject to the model outputs. A graphical interface is used to specify and validate a timing diagram.