High level testbench generation for VHDL models

Authors:
Stanislaw Deniziak;Krzysztof Sapiecha
Affiliations:
Cracow University of Technology, Department of Computer Engineering, Cracow, Poland;Cracow University of Technology, Department of Computer Engineering, Cracow, Poland
Venue:
ECBS'99 Proceedings of the 1999 IEEE conference on Engineering of computer-based systems
Year:
1999

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Abstract

In this paper, a new technique of automatic generation of VHDL testbenches is presented. Testbenches are generated using stimuli description in the WEGA language [16] and VHDL entity declaration of the model under test. This technique makes it possible to reduce the length and complexity of testbenches by the factor of 10, on average. Moreover, describing testbenches in WEGA is much easier and flexible than describing them directly in VHDL. The source WEGA code is also more readable.