An engineering environment for hardware/software co-simulation
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Accelerating concurrent hardware design with behavioural modelling and system simulation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Cosimulation of real-time control systems
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
How to efficiently build VHDL testbenches
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Software development in a hardware simulation environment
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
CoWare—a design environment for heterogenous hardware/software systems
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
HW/SW coverification performance estimation and benchmark for a 24 embedded RISC core design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Towards efficient design space exploration of heterogeneous embedded media systems
Embedded processor design challenges
Re-use-centric architecture for a fully accelerated testbench environment
Proceedings of the 40th annual Design Automation Conference
Platform-Based Testbench Generation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Layered Adaptive Verification Platform for Simulation, Test, and Emulation
IEEE Design & Test
Software-friendly HW/SW co-simulation: an industrial case study
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
High level testbench generation for VHDL models
ECBS'99 Proceedings of the 1999 IEEE conference on Engineering of computer-based systems
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Novel test bench techniques are required to cope with afunctional test complexity which is predicted to grow muchmore strongly than design complexity. Our test benchapproach attacks this complexity by using a stronghierarchical architecture, application domain-independentsynchronization, reusable modules, and easy incrementalextendability based on table-driven techniques. In addition,the integration of VHDL/C co-simulation under the controlof the test bench makes it possible to use the hardware modelfor software testing and vice versa and thus enables extremereductions in test bench coding. The efficiency of our testbench has already been demonstrated in several industrialprojects, among them a four-ASIC ATM board with oneembedded core and one external micro controller.