Computer organization & design: the hardware/software interface
Computer organization & design: the hardware/software interface
How to efficiently build VHDL testbenches
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Hardware/software co-simulation in a VHDL-based test bench approach
DAC '97 Proceedings of the 34th annual Design Automation Conference
Bit-Slice Design Controllers and Alu's
Bit-Slice Design Controllers and Alu's
An integrated environment for HDL verification
IVC '95 Proceedings of the 4th IEEE International Verilog HDL Conference
Re-use-centric architecture for a fully accelerated testbench environment
Proceedings of the 40th annual Design Automation Conference
A novel SoC platform based multi-IP verification and performance measurement
International Journal of Information and Communication Technology
A novel multi-IP verification methodology using an SoC platform
ACST '08 Proceedings of the Fourth IASTED International Conference on Advances in Computer Science and Technology
| Hi-index | 0.00 |
This paper presents a new technology that accelerates system verification. In a real life example, we achieved a speed-up of a factor of about 5000. The key for this speed-up is a configurable, synthesizable testbench architecture, which can be completely mapped to emulators or FPGAs. Exploiting generic controllers and re-using protocol-specific stimuli generators combined with topology and micro-program generation is responsible for almost zero overhead compared to behavioral testbenches.