Proceedings of the international workshop on Automatic verification methods for finite state systems
Synchronous circuit verification by symbolic simulation: an illustration
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
Formal hardware verification methods: a survey
Formal Methods in System Design - Special issue on computer-aided verification: general methods
A methodology for formal hardware verification, with application to microprocessors
A methodology for formal hardware verification, with application to microprocessors
HSIS: a BDD-based environment for formal verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Interleaving based variable ordering methods for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Analysis of cyclic combinational circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Formal Verification of VHDL Descriptions in the Prevail Environment
IEEE Design & Test
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Efficient implementation of the smalltalk-80 system
POPL '84 Proceedings of the 11th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories
Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories
Platform-Based Testbench Generation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Layered Adaptive Verification Platform for Simulation, Test, and Emulation
IEEE Design & Test
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The functional verification of a digital design is an expensive step in the design process. As designs become more complex, simulation is challenged throughout the design and verification process, both at the low level (implementation verification), to show that a low level implementation implements a higher-level specification, and at the high level (design verification), to show that a design complies with some abstract specification. In both areas, formal methods can extend the reach of simulation: for implementation verification, equivalence checking is used to show that two circuits are functionally the same in some well defined sense. For design verification, model checking and other property checking techniques serve as a smart simulator. This paper describes Forte, a formal verification prototype that integrates formal verification and simulation. Forte fits into a standard top-down design flow using standard HDL's such as Verilog-HDL and VHDL, and works well with synthesis. Forte includes traditional and symbolic simulation, combinational and sequential equivalence, and CTL model checking. We discuss its design and implementation, and illustrate the utility of combining formal verification and simulation using an example. Moreover, Forte's object-oriented design makes it an ideal platform for rapidly evaluating new ideas in verification.