Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
A computational logic handbook
A computational logic handbook
Communication and concurrency
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
A unified approach to language containment and fair CTL model checking
DAC '93 Proceedings of the 30th international Design Automation Conference
BDD variable ordering for interacting finite state machines
DAC '94 Proceedings of the 31st annual Design Automation Conference
Modalities for model checking (extended abstract): branching time strikes back
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Symbolic Model Checking
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Efficient omega-Regular Language Containment
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Verilog HDL Modeling Styles for Formal Verification
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
BDD-Based Debugging Of Design Using Language Containment and Fair CTL
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Edge-Streett/ Edge-Rabin Automata Environment for
Edge-Streett/ Edge-Rabin Automata Environment for
Heuristic Algorithms for Early Quantification and Partial
Heuristic Algorithms for Early Quantification and Partial
Iterative algorithms for formal verification of embedded real-time systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Incremental formal design verification
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
BDD variable ordering for interacting finite state machines
DAC '94 Proceedings of the 31st annual Design Automation Conference
Model checking in industrial hardware design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Symbolic modeling and evaluation of data paths
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Auxiliary variables for BDD-based representation and manipulation of Boolean functions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Polynomial Formal Verification of Multipliers
Formal Methods in System Design
Design Verification of FPGA Implementations
IEEE Design & Test
Comparing HOL and MDG: a case study on the verification of an ATM switch fabric
Nordic Journal of Computing
A HOL Conversion for Translating Linear Time Temporal Logic to omega-Automata
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Formal Verification of Digital Systems
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Polynomial Formal Verification of Multipliers
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Compiling Verilog into timed finite state machines
IVC '95 Proceedings of the 4th IEEE International Verilog HDL Conference
An integrated environment for HDL verification
IVC '95 Proceedings of the 4th IEEE International Verilog HDL Conference
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