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Journal of the ACM (JACM) - The MIT Press scientific computation series
Automatic Verification of Sequential Circuits Using Temporal Logic
IEEE Transactions on Computers
Parallel program design: a foundation
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Handbook of theoretical computer science (vol. B)
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Introduction to HOL: a theorem proving environment for higher order logic
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HSIS: a BDD-based environment for formal verification
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An automata-theoretic approach to linear temporal logic
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IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
CTL and equivalent sublanguages of CTL
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Symbolic Model Checking
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TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
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HUG '93 Proceedings of the 6th International Workshop on Higher Order Logic Theorem Proving and its Applications
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HUG '93 Proceedings of the 6th International Workshop on Higher Order Logic Theorem Proving and its Applications
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CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
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CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
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CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
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HOL'92 Proceedings of the IFIP TC10/WG10.2 Workshop on Higher Order Logic Theorem Proving and its Applications
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SFCS '88 Proceedings of the 29th Annual Symposium on Foundations of Computer Science
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TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
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CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
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CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
PROSPER - An Investigation into Software Architecture for Embedded Proof Engines
FroCoS '02 Proceedings of the 4th International Workshop on Frontiers of Combining Systems
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
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TPHOLs '09 Proceedings of the 22nd International Conference on Theorem Proving in Higher Order Logics
From PSL to LTL: a formal validation in HOL
TPHOLs'05 Proceedings of the 18th international conference on Theorem Proving in Higher Order Logics
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SBMF'12 Proceedings of the 15th Brazilian conference on Formal Methods: foundations and applications
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We present an embedding of linear time temporal logic LTL in HOL together with an elegant translation of LTL formulas into equivalent ω-automata. The translation is completely implemented by HOL rules and is therefore safe. Its implementation is mainly based on preproven theorems such that the conversion works very efficiently. In particular, it runs in linear time in terms of the given formula. The main application of this conversion is the sound integration of symbolic model checkers as (unsafe) decision procedures in the HOL theorem prover. On the other hand, the conversion also enables HOL users to directly verify temporal properties by means of HOL's induction rules.