A refinement calculus for the synthesis of verified hardware descriptions in VHDL
ACM Transactions on Programming Languages and Systems (TOPLAS)
Formal specification in VHDL for hardware verification
Proceedings of the conference on Design, automation and test in Europe
Improving Automata Generation for Linear Temporal Logic by Considering the Automaton Hierarchy
LPAR '01 Proceedings of the Artificial Intelligence on Logic for Programming
A HOL Conversion for Translating Linear Time Temporal Logic to omega-Automata
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Modleing and Checking Networks of Communicating Real-Time Process
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Symbolic Verification and Analysis of Discrete Timed Systems
Formal Methods in System Design
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