Handbook of theoretical computer science (vol. B)
Handbook of theoretical computer science (vol. B)
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Formal hardware verification methods: a survey
Formal Methods in System Design - Special issue on computer-aided verification: general methods
Denotational semantics of a synchronous VHDL subset
Formal Methods in System Design - Special issue on VHDL semantics
Specification and verification of VHDL-based system-level hardware designs
Specification and validation methods
CTL and equivalent sublanguages of CTL
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Verification of VHDL designs using VAL
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Symbolic Model Checking
Formal Semantics for VHDL
IEEE Standards Intepretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual
IEEE Standards Intepretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual
Studies of the Single Pulser in Various Reasoning Systems
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
Benchmark-Circuits for Hardware-Verification
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
Formal Specification and Verification of VHDL
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
A Unified Approach for Combining Different Formalisms for Hardware Verification
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Verifying VHDL Designs with COSPAN
Formal Hardware Verification - Methods and Systems in Comparison
Evaluating possibilities for formally sound simulation and verification of VHDL
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
From PSL to LTL: a formal validation in HOL
TPHOLs'05 Proceedings of the 18th international conference on Theorem Proving in Higher Order Logics
| Hi-index | 0.00 |
In this paper, we enrich VHDL with new specification constructs intended for hardware verification. Using our extensions, total correctness properties may now be stated whereas only partial correctness can be expressed using the standard VHDL assert statement. All relevant properties can now be specified in such a way that the designer does not need to use formalisms like temporal logics. As the specifications are independent from a certain formalism, there is no restriction to a certain hardware verification approach.