A native process algebra for VHDL
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A refinement calculus for the synthesis of verified hardware descriptions in VHDL
ACM Transactions on Programming Languages and Systems (TOPLAS)
Reasoning about VHDL and VHDL-AMS using denotational semantics
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The simulation semantics of systemC
Proceedings of the conference on Design, automation and test in Europe
Formal specification in VHDL for hardware verification
Proceedings of the conference on Design, automation and test in Europe
Structural Operational Semantics for a Portable Subset of Behavioral VHDL-93
Formal Methods in System Design
The formal execution semantics of SpecC
Proceedings of the 15th international symposium on System Synthesis
Verifying the FM9801 Microarchitecture
IEEE Micro
Combined Formal Post- and Presynthesis Verification in High Level Synthesis
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
IFM '00 Proceedings of the Second International Conference on Integrated Formal Methods
SystemC
Formal Semantics of Synchronous SystemC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Toward a semantic anchoring infrastructure for domain-specific modeling languages
Proceedings of the 5th ACM international conference on Embedded software
Formal specification and analysis of hardware systems in timed Chi
Nordic Journal of Computing
A monadic approach to automated reasoning for Bluespec SystemVerilog
Innovations in Systems and Software Engineering
An algebraic approach for codesign
ICTAC'04 Proceedings of the First international conference on Theoretical Aspects of Computing
Combining several paradigms for circuit validation and verification
CASSIS'04 Proceedings of the 2004 international conference on Construction and Analysis of Safe, Secure, and Interoperable Smart Devices
A dynamic hardware generation mechanism based on partial evaluation
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
Evaluating possibilities for formally sound simulation and verification of VHDL
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
A logic to specify and verify synchronous transitions
IW-FM'99 Proceedings of the 3rd Irish conference on Formal Methods
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From the Publisher:It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several commercially- and academically-based tools. Having different tools and users generating and reading the same language requires that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a descriptive way, explaining the semantics in English. But rigor and clarity is very hard to maintain in a semantics defined in this way, and that has already given rise to many misconceptions and contradictory interpretations. Formal Semantics for VHDL is the first book that puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism: two of them use Petri nets as target language, and two of them higher order logic. Two use functional concepts, and finally another uses the concept of evolving algebras. Formal Semantics for VHDL is essential reading for researchers in Formal Methods and can be used as a text for an advanced course on the subject.