The semantics of programming languages: an elementary introduction using structural operational semantics
A VHDL primer
The formal semantics of programming languages: an introduction
The formal semantics of programming languages: an introduction
Formal Methods in System Design - Special issue on VHDL semantics
Characterizing a portable subset of behavioral VHDL-93
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
Formal Semantics for VHDL
Introduction To Automata Theory, Languages, And Computation
Introduction To Automata Theory, Languages, And Computation
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Semantics of a verification-oriented subset of VHDL
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Reasoning about VHDL using operational and observational semantics
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
A polymodal semantics for VHDL
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Information flow analysis for VHDL
PaCT'05 Proceedings of the 8th international conference on Parallel Computing Technologies
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Goossens defined structural operational semantics for a subset of VHDL-87 and proved that the parallelism present in VHDL is benign. We extend this work to include VHDL-93 features such as shared variables and postponed processes that change the underlying semantic model. In the presence of shared variables, non-deterministic execution of VHDL-93 processes destroys the unique meaning property. We identify and characterize a class of portable VHDL-93 descriptions for which unique meaning property can be salvaged. We analyze the computability of the portability condition and show that portability checks are neither local nor static. Our formal specification can serve as a correctness criteria for a VHDL-93 simulator or can be used as a basis for coding a simulator.