A native process algebra for VHDL
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A refinement calculus for VHDL
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A refinement calculus for the synthesis of verified hardware descriptions in VHDL
ACM Transactions on Programming Languages and Systems (TOPLAS)
Reasoning about VHDL and VHDL-AMS using denotational semantics
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Structural Operational Semantics for a Portable Subset of Behavioral VHDL-93
Formal Methods in System Design
Formal Semantics of Synchronous SystemC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Evaluating possibilities for formally sound simulation and verification of VHDL
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
A logic to specify and verify synchronous transitions
IW-FM'99 Proceedings of the 3rd Irish conference on Formal Methods
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