Formal Methods in System Design - Special issue on VHDL semantics
Denotational semantics of a synchronous VHDL subset
Formal Methods in System Design - Special issue on VHDL semantics
The simulation semantics of systemC
Proceedings of the conference on Design, automation and test in Europe
Principles of Programming Languages
Principles of Programming Languages
The Denotational Description of Programming Languages: An Introduction
The Denotational Description of Programming Languages: An Introduction
Formal Semantics for VHDL
The Verilog Hardware Description Language, 5th Edition
The Verilog Hardware Description Language, 5th Edition
Formal Verification of VHDL Descriptions in the Prevail Environment
IEEE Design & Test
SystemC
A Schedulerless Semantics of TLM Models Written in SystemC Via Translation into LOTOS
FM '08 Proceedings of the 15th international symposium on Formal Methods
Model checking SystemC designs using timed automata
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Combining Model Checking and Testing in a Continuous HW/SW Co-verification Process
TAP '09 Proceedings of the 3rd International Conference on Tests and Proofs
On the Transformation of SystemC to AsmL Using Abstract Interpretation
Electronic Notes in Theoretical Computer Science (ENTCS)
Race analysis for systemc using model checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A systemC/TLM semantics in PROMELA and its possible applications
Proceedings of the 14th international SPIN conference on Model checking software
Compositional semantics of system-level designs written in systemC
FSEN'07 Proceedings of the 2007 international conference on Fundamentals of software engineering
Sysfier: Actor-based formal verification of SystemC
ACM Transactions on Embedded Computing Systems (TECS)
UTP'08 Proceedings of the 2nd international conference on Unifying theories of programming
Design and verification of systemc transaction-level models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Building SystemC waiting state automata
VECoS'11 Proceedings of the Fifth international conference on Verification and Evaluation of Computer and Communication Systems
A HW/SW co-verification framework for SystemC
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
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In this article, a denotational definition of synchronous subset of SystemC is proposed. The subset treated includes modules, processes, threads, wait statement, ports and signals. We propose formal model for System C delta delay. Also, we give a complete semantic definition for the languageýs two-phase scheduler. The proposed semantic can constitute a base for validating the equivalence of synchronous HDL subsets.