Theoretical Computer Science
UPPAAL—a tool suite for automatic verification of real-time systems
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
The simulation semantics of systemC
Proceedings of the conference on Design, automation and test in Europe
System Design with SystemC
Formal Semantics of Synchronous SystemC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
HW/SW co-verification of embedded systems using bounded model checking
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Generating finite state machines from SystemC
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Formal verification of systemc designs using a petri-net based representation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
SC2SCFL: automated systemC to systemCFLtranslation
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
An approach for the verification of systemc designs using asml
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Combining Model Checking and Testing in a Continuous HW/SW Co-verification Process
TAP '09 Proceedings of the 3rd International Conference on Tests and Proofs
Formal and executable contracts for transaction-level modeling in SystemC
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
A framework for verification of software with time and probabilities
FORMATS'10 Proceedings of the 8th international conference on Formal modeling and analysis of timed systems
Verifying SystemC: a software model checking approach
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
KRATOS: a software model checker for SystemC
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
An analytic evaluation of SystemC encodings in Promela
Proceedings of the 18th international SPIN conference on Model checking software
Relating average and discounted costs for quantitative analysis of timed systems
EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software
Symbolic model checking on SystemC designs
Proceedings of the 49th Annual Design Automation Conference
Formal Analysis of SystemC Designs in Process Algebra
Fundamenta Informaticae
A HW/SW co-verification framework for SystemC
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Verifying SystemC using an intermediate verification language and symbolic simulation
Proceedings of the 50th Annual Design Automation Conference
Conquering the scheduling alternative explosion problem of SystemC symbolic simulation
Proceedings of the International Conference on Computer-Aided Design
A Semantics-based Translation Method for Automated Verification of SystemC TLM Designs
Journal of Electronic Testing: Theory and Applications
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SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In this paper, we present an approach to overcome this problem by defining the semantics of SystemC by a mapping from SystemC designs into the well-defined semantics of Uppaal timed automata. The informally defined behavior and the structure of SystemC designs are completely preserved in the generated Uppaal models. The resulting Uppaal models allow us to use the Uppaal model checker and the Uppaal tool suite, including simulation and visualization tools. The model checker can be used to verify important properties such as liveness, deadlock freedom or compliance with timing constraints. We have implemented the presented transformation, applied it to two examples and verified liveness, safety and timing properties by model checking, thus showing the applicability of our approach in practice.