Model checking
SPIN Tutorial: How to Become a SPIN Doctor
Proceedings of the 9th International SPIN Workshop on Model Checking of Software
NUSMV: A New Symbolic Model Verifier
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Formal verification of SystemC by automatic hardware/software partitioning
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Model checking SystemC designs using timed automata
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A systemC/TLM semantics in PROMELA and its possible applications
Proceedings of the 14th international SPIN conference on Model checking software
Boosting lazy abstraction for systemc with partial order reduction
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Verifying SystemC: a software model checking approach
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
An analytic evaluation of SystemC encodings in Promela
Proceedings of the 18th international SPIN conference on Model checking software
Automatic RTL Test Generation from SystemC TLM Specifications
ACM Transactions on Embedded Computing Systems (TECS)
Symbolic model checking on SystemC designs
Proceedings of the 49th Annual Design Automation Conference
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SystemC has become a de-facto standard language for SoC and ASIP designs. The verification of implementation with SystemC is the key to guarantee the correctness of designs and prevent the errors from propagating to the lower levels. In this project, we attempt translate SystemC programs to formal models and use existing model checkers to implement the verification. The method we proposed is based on a semantic translation method which translates sequential execution statements described as software character to parallel execution ones which are more closely with the implementation of hardware. This kind of conversion is inevitable to verify hardware designs but is overlooked in related works. The main contribution of this work is a translation method which can preserve the semantic consistency while building SMV model for SystemC design. We present the translation rules and implement a prototype tool which supports a subset of SystemC to demonstrate the effectiveness of our method.