Embedded tutorial: formal equivalence checking between system-level models and RTL
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Formal verification of systemc designs using a petri-net based representation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Verification of SpecC using predicate abstraction
Formal Methods in System Design
Model-driven validation of SystemC designs
Proceedings of the 44th annual Design Automation Conference
Partial order reduction for scalable testing of systemC TLM designs
Proceedings of the 45th annual Design Automation Conference
A Schedulerless Semantics of TLM Models Written in SystemC Via Translation into LOTOS
FM '08 Proceedings of the 15th international symposium on Formal Methods
Model-driven validation of SystemC designs
EURASIP Journal on Embedded Systems - C-Based Design of Heterogeneous Embedded Systems
Race analysis for SystemC using model checking
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A temporal language for SystemC
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Full simulation coverage for SystemC transaction-level models of systems-on-a-chip
Formal Methods in System Design
Verification of an industrial systemC/TLM model using LOTOS and CADP
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Race analysis for systemc using model checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A systemC/TLM semantics in PROMELA and its possible applications
Proceedings of the 14th international SPIN conference on Model checking software
Compositional semantics of system-level designs written in systemC
FSEN'07 Proceedings of the 2007 international conference on Fundamentals of software engineering
Reactivity in systemC transaction-level models
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
Scoot: a tool for the analysis of SystemC models
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Sysfier: Actor-based formal verification of SystemC
ACM Transactions on Embedded Computing Systems (TECS)
A framework for verification of software with time and probabilities
FORMATS'10 Proceedings of the 8th international conference on Formal modeling and analysis of timed systems
Verifying SystemC: a software model checking approach
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Path predicate abstraction by complete interval property checking
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
KRATOS: a software model checker for SystemC
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
An analytic evaluation of SystemC encodings in Promela
Proceedings of the 18th international SPIN conference on Model checking software
SystemC waiting state automata
International Journal of Critical Computer-Based Systems
Formalizing hardware/software interface specifications
ASE '11 Proceedings of the 2011 26th IEEE/ACM International Conference on Automated Software Engineering
Automatic RTL Test Generation from SystemC TLM Specifications
ACM Transactions on Embedded Computing Systems (TECS)
SystemC waiting-state automata
VECoS'07 Proceedings of the First international conference on Verification and Evaluation of Computer and Communication Systems
Building SystemC waiting state automata
VECoS'11 Proceedings of the Fifth international conference on Verification and Evaluation of Computer and Communication Systems
Symbolic model checking on SystemC designs
Proceedings of the 49th Annual Design Automation Conference
System verification of concurrent RTL modules by compositional path predicate abstraction
Proceedings of the 49th Annual Design Automation Conference
Formal Analysis of SystemC Designs in Process Algebra
Fundamenta Informaticae
Verifying SystemC using an intermediate verification language and symbolic simulation
Proceedings of the 50th Annual Design Automation Conference
Facilitating the design of fault tolerance in transaction level SystemC programs
Theoretical Computer Science
Conquering the scheduling alternative explosion problem of SystemC symbolic simulation
Proceedings of the International Conference on Computer-Aided Design
Automatic Generation of System Level Assertions from Transaction Level Models
Journal of Electronic Testing: Theory and Applications
A Semantics-based Translation Method for Automated Verification of SystemC TLM Designs
Journal of Electronic Testing: Theory and Applications
Colored Petri Net model with automatic parallelization on real-time multicore architectures
Journal of Systems Architecture: the EUROMICRO Journal
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Variants of general-purpose programming languages, like SystemC, are increasingly used to specify system designs that have both hardware and software parts. The system-level languages allow a flexible partitioning in the design of the hardware and software. Moreover, many properties depend on the combination of hardware and software and cannot be verified on either part alone. Existing tools either apply non-formal approaches or handle only the low-level parts of the language. This papers presents a new technique that handles both hardware and software parts of a system description. This is done by automatically partitioning the uniform system description into synchronous (hardware) and asynchronous (software) parts. This technique has been implemented and applied to system level descriptions of several industrial examples. The hardware/software partitioning improves the performance of the verification compared to the monolithic approach.