IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
SystemC: a homogenous environment to test embedded systems
Proceedings of the ninth international symposium on Hardware/software codesign
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Automating the Addition of Fault-Tolerance
FTRTFT '00 Proceedings of the 6th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
LusSy: A Toolbox for the Analysis of Systems-on-a-Chip at the Transactional Level
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
Automatic synthesis of fault-tolerance
Automatic synthesis of fault-tolerance
Exploiting Symbolic Techniques in Automated Synthesis of Distributed Programs with Large State Space
ICDCS '07 Proceedings of the 27th International Conference on Distributed Computing Systems
Fault Injection Techniques and their Accelerated Simulation in SystemC
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Formal verification of SystemC by automatic hardware/software partitioning
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Partial order reduction for scalable testing of systemC TLM designs
Proceedings of the 45th annual Design Automation Conference
FTSyn: a framework for automatic synthesis of fault-tolerance
International Journal on Software Tools for Technology Transfer (STTT)
SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
Model-driven validation of SystemC designs
EURASIP Journal on Embedded Systems - C-Based Design of Heterogeneous Embedded Systems
Multi-level fault modeling for transaction-level specifications
Proceedings of the 19th ACM Great Lakes symposium on VLSI
On the Use of Dynamic Binary Instrumentation to Perform Faults Injection in Transaction Level Models
DEPCOS-RELCOMEX '09 Proceedings of the 2009 Fourth International Conference on Dependability of Computer Systems
Race analysis for systemc using model checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A systemC/TLM semantics in PROMELA and its possible applications
Proceedings of the 14th international SPIN conference on Model checking software
Mutation Operators for Concurrent SystemC Designs
MTV '09 Proceedings of the 2009 10th International Workshop on Microprocessor Test and Verification
Codesign and Simulated Fault Injection of Safety-Critical Embedded Systems Using SystemC
EDCC '10 Proceedings of the 2010 European Dependable Computing Conference
PinaVM: a systemC front-end based on an executable intermediate representation
EMSOFT '10 Proceedings of the tenth ACM international conference on Embedded software
KRATOS: a software model checker for SystemC
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
An analytic evaluation of SystemC encodings in Promela
Proceedings of the 18th international SPIN conference on Model checking software
Feasibility of Stepwise Design of Multitolerant Programs
ACM Transactions on Software Engineering and Methodology (TOSEM)
Fault models and test generation for hardware-software covalidation
IEEE Design & Test
Modeling and analyzing timing faults in transaction level SystemC programs
Proceedings of the Sixth International Workshop on Network on Chip Architectures
| Hi-index | 5.23 |
Due to their increasing complexity, today's SoC (system on chip) systems are subject to a variety of faults (e.g., single-event upset, component crash, etc.), thereby making fault tolerance a highly important property of such systems. However, designing fault tolerance is a complex task in part due to the large scale of integration of SoC systems and different levels of abstraction provided by modern system design languages such as SystemC. Most existing methods enable fault injection and impact analysis as a means for increasing design dependability. Nonetheless, such methods provide little support for designing fault tolerance. To facilitate the design of fault tolerance in SoC systems, this paper proposes an approach for designing fault-tolerant inter-component communication protocols in SystemC transaction level modeling (TLM) programs. The proposed method includes four main steps, namely model extraction, fault modeling, addition of fault tolerance and refinement of fault tolerance to SystemC code. We demonstrate the proposed approach using a simple SystemC transaction level program that is subject to communication faults. Moreover, we illustrate how fault tolerance can be added to SystemC programs that use the base protocol of the TLM interoperability layer. We also illustrate how fault tolerance functionalities can be partitioned to software and hardware components. Finally, we put forward a roadmap for future research at the intersection of fault tolerance and hardware-software co-design.