Multi-level fault modeling for transaction-level specifications

Authors:
Giovanni Beltrame;Cristiana Bolchini;Antonio Miele
Affiliations:
European Space Agency, Noordwijk, Netherlands;Politecnico di Milano, Milano, Italy;Politecnico di Milano, Milano, Italy
Venue:
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Year:
2009

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Abstract

Fault modeling is a fundamental element for several activities, ranging from off- and on-line testing, to fault tolerance and dependability-aware design. These activities are carried out during various design phases, dealing with specifications at different abstraction levels. Therefore, modeling faults across abstraction levels is of paramount importance to introduce dependability-related issues from the early phases of design. This paper analyzes how faults can be modeled at the different levels of abstraction with respect to Transaction Level Models, and how these models are related across levels. The work focuses on soft errors and aims at providing support to dependability analysis. A case study of a Transaction Level specification of a Network-on-Chip switch is used to evaluate the methodology and its applicability.