Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Design for verification in system-level models and RTL
Proceedings of the 44th annual Design Automation Conference
Leveraging sequential equivalence checking to enable system-level to RTL flows
Proceedings of the 45th annual Design Automation Conference
Multi-level fault modeling for transaction-level specifications
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Simulation-based equivalence checking between SystemC models at different levels of abstraction
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
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It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). These models are written in C++ primarily because it is possible to achieve very high simulation speeds, but also because it is productive to code at high levels of abstraction. In this paper we present a modeling methodology that continues to exploit the inherent advantages of writing models in C++ while ensuring that they are usable for formal verification of RTL through the use of sequential equivalence checking technology. An industrial case study is presented to show the validity of the approach.