A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example

Authors:
W. M. Young;Chua-Huang Huang;Alan P. Su;C. P. Jou;Fu-Lung Hsueh
Affiliations:
TSMC, Hsinchu, Taiwan;Feng Chia University, Taichung, Taiwan;Global Unichip Corp., Hsinchu, Taiwan;TSMC, Hsinchu, Taiwan;TSMC, Hsinchu, Taiwan
Venue:
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Year:
2010

Citing 11
Cited 1

Architectural partitioning for system level design

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Dynamic hardware/software partitioning: a first approach

Proceedings of the 40th annual Design Automation Conference
Transaction level modeling: an overview

Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration

Proceedings of the 42nd annual Design Automation Conference
Use of C/C++ models for architecture exploration and verification of DSPs

Proceedings of the 43rd annual Design Automation Conference
Maintaining consistency between systemC and RTL system designs

Proceedings of the 43rd annual Design Automation Conference
SystemC transaction level models and RTL verification

Proceedings of the 43rd annual Design Automation Conference
Towards a C++-based design methodology facilitating sequential equivalence checking

Proceedings of the 43rd annual Design Automation Conference
Building a standard ESL design and verification methodology: is it just a dream?

Proceedings of the 43rd annual Design Automation Conference
Verification methodologies in a TLM-to-RTL design flow

Proceedings of the 44th annual Design Automation Conference
Predictive runtime verification of multi-processor SoCs in SystemC

Proceedings of the 45th annual Design Automation Conference

Co-simulation framework of SystemC SoC virtual prototype and custom logic (abstract only)

Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents the first published industrial practice (to the best of our knowledge) to reuse high-level/C++ system simulation model through OSCI TLM 2.0 Library to verify its corresponding RTL implementation in FPGA. ESL verification methodology is employed in the design regression of EPC C1Gen2 RFID tag. Around 200 times speedup is observed using ESL over conventional RTL simulation in regression runs (after logic bug fixes). This clearly shows ESL verification is a successful candidate to reuse high-level test harness for IC functional verification, especially in today's increasingly complex IC design world. On top of the successful use of the ESL functional verification flow on the design, we also show the infrastructure to use SystemC Verification Library (SCV) for formal verification. The functional and formal verification combined is thus the proposed ESL verification methodology.