Verification methodologies in a TLM-to-RTL design flow

Authors:
Atsushi Kasuya;Tesh Tesfaye
Affiliations:
JEDA Technologies Inc., Los Altos, CA;JEDA Technologies Inc., Los Altos, CA
Venue:
Proceedings of the 44th annual Design Automation Conference
Year:
2007

Citing 0
Cited 8

Predictive runtime verification of multi-processor SoCs in SystemC

Proceedings of the 45th annual Design Automation Conference
A pointcut-based assertion for high-level hardware design

Proceedings of the 2008 AOSD workshop on Aspects, components, and patterns for infrastructure software
A temporal language for SystemC

Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
MAGENTA: transaction-based statistical micro-architectural root-cause analysis

Proceedings of the 46th Annual Design Automation Conference
A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
ASystemC: an AOP extension for hardware description language

Proceedings of the tenth international conference on Aspect-oriented software development companion
Concurrency-oriented verification and coverage of system-level designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Transaction level statistical analysis for efficient micro-architectural power and performance studies

Proceedings of the 48th Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

SoC based system developments commonly employ ESL design methodologies and utilize multiple levels of abstract models to provide feasibility study models for architects and development platforms for software engineers. Such models are evolving to finer abstract models as the development moves forward. The correctness of these models coupled with the ability of having a temporal debug environment to identify and fix model issues is critical for both hardware and software development efforts that make use of such models. This paper presents the mechanism to construct temporal assertions at models in various abstract levels and reuse the assertions on models at different abstract level.