All-uses vs mutation testing: an experimental comparison of effectiveness
Journal of Systems and Software
DAC '98 Proceedings of the 35th annual Design Automation Conference
High-level design verification of microprocessors via error modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dynamic state traversal for sequential circuit test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Programmers use slices when debugging
Communications of the ACM
Time, clocks, and the ordering of events in a distributed system
Communications of the ACM
Elements of distributed computing
Elements of distributed computing
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Computation Slicing: Techniques and Theory
DISC '01 Proceedings of the 15th International Conference on Distributed Computing
Concurrent Bug Patterns and How to Test Them
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
A measure of test case completeness (software, engineering)
A measure of test case completeness (software, engineering)
Runtime safety analysis of multithreaded programs
Proceedings of the 9th European software engineering conference held jointly with 11th ACM SIGSOFT international symposium on Foundations of software engineering
Is mutation an appropriate tool for testing experiments?
Proceedings of the 27th international conference on Software engineering
MuJava: an automated class mutation system: Research Articles
Software Testing, Verification & Reliability
Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Mutation Operators for Concurrent Java (J2SE 5.0)
MUTATION '06 Proceedings of the Second Workshop on Mutation Analysis
Mutation Testing implements Grammar-Based Testing
MUTATION '06 Proceedings of the Second Workshop on Mutation Analysis
Formal Verification of Simulation Traces Using Computation Slicing
IEEE Transactions on Computers
Interactive presentation: Implementation of a transaction level assertion framework in SystemC
Proceedings of the conference on Design, automation and test in Europe
Formal techniques for SystemC verification
Proceedings of the 44th annual Design Automation Conference
Verification methodologies in a TLM-to-RTL design flow
Proceedings of the 44th annual Design Automation Conference
Leveraging a Commercial Mutation Analysis Tool For Research
TAICPART-MUTATION '07 Proceedings of the Testing: Academic and Industrial Conference Practice and Research Techniques - MUTATION
Too Few or Too Many Properties? Measure it by ATPG!
Journal of Electronic Testing: Theory and Applications
Partial order reduction for scalable testing of systemC TLM designs
Proceedings of the 45th annual Design Automation Conference
Predictive runtime verification of multi-processor SoCs in SystemC
Proceedings of the 45th annual Design Automation Conference
A mutation model for the SystemC TLM 2.0 communication interfaces
Proceedings of the conference on Design, automation and test in Europe
A Tractable and Fast Method for Monitoring SystemC TLM Specifications
IEEE Transactions on Computers
A temporal language for SystemC
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
A theory of mutations with applications to vacuity, coverage, and fault tolerance
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Can Mutation Analysis Help Fix Our Broken Coverage Metrics?
HVC '08 Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing
ICSTW '09 Proceedings of the IEEE International Conference on Software Testing, Verification, and Validation Workshops
Full simulation coverage for SystemC transaction-level models of systems-on-a-chip
Formal Methods in System Design
Race analysis for systemc using model checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Defining and Providing Coverage for Assertion-Based Dynamic Verification
Journal of Electronic Testing: Theory and Applications
Functional qualification of TLM verification
Proceedings of the Conference on Design, Automation and Test in Europe
Assertion-Based Design
Verification and coverage of message passing multicore applications
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Generation of TLM testbenches using mutation testing
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Completeness-driven development
ICGT'12 Proceedings of the 6th international conference on Graph Transformations
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Correct concurrent System-on-Chips (SoCs) are very hard to design and reason about. In this work, we develop an automated framework complete with concurrency-oriented verification and coverage techniques for system-level designs. Our techniques are different from traditional simulation-based reliability techniques, since concurrency information is often lost in traditional techniques. We preserve concurrency information to obtain unique verification techniques that allow us to predict potential errors (formulated as transaction-level assertions) from error-free simulations. In order to do this, we exploit the inherent concurrency in the designs to generate and analyze novel partial-order simulation traces. Additionally, to evaluate the confidence on verification results and the gauge progress of verification, we develop novel mutation testing based on concurrent coverage metrics. Mutation testing is a fault insertion-based simulation technique that has been successfully applied in software testing. We present a comprehensive list of mutation operators for SystemC, similar to behavioral fault models, and show the effectiveness of these operators by relating them to actual bug patterns. We have successfully applied our verification and coverage techniques on industrial systems and demonstrated that current verification test suites need to be improved for concurrent designs, and we have found errors in systems that were tested previously.