Towards an efficient assertion based verification of SystemC designs
HLDVT '04 Proceedings of the High-Level Design Validation and Test Workshop, 2004. Ninth IEEE International
Predictive runtime verification of multi-processor SoCs in SystemC
Proceedings of the 45th annual Design Automation Conference
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Formal semantics for PSL modeling layer and application to the verification of transactional models
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Proceedings of the Conference on Design, Automation and Test in Europe
Verifying SystemC using an intermediate verification language and symbolic simulation
Proceedings of the 50th Annual Design Automation Conference
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Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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Current hardware design and verification methodologies reflect a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Since transaction level models (TLMs) are used for early prototyping and as reference models for the verification of their RTL representation, the quality assurance of TLMs is vital. Assertion based verification (ABV) of RTL models has improved quality assurance of IP blocks and SoC systems to a great extent. Since mapping of an RTL ABV methodology to TL poses severe problems due to different design paradigms, current ABV approaches need extensions towards TL. In this paper we present a prototype implementation of a TL assertion framework using SystemC which is currently the de facto standard for system modeling.