Logical Time in Distributed Computing Systems
Computer - Distributed computing systems: separate resources acting as one
Time, clocks, and the ordering of events in a distributed system
Communications of the ACM
Runtime safety analysis of multithreaded programs
Proceedings of the 9th European software engineering conference held jointly with 11th ACM SIGSOFT international symposium on Foundations of software engineering
LusSy: A Toolbox for the Analysis of Systems-on-a-Chip at the Transactional Level
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
Proceedings of the 2006 workshop on Parallel and distributed systems: testing and debugging
Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Formal Verification of Simulation Traces Using Computation Slicing
IEEE Transactions on Computers
Interactive presentation: Implementation of a transaction level assertion framework in SystemC
Proceedings of the conference on Design, automation and test in Europe
Formal techniques for SystemC verification
Proceedings of the 44th annual Design Automation Conference
Verification methodologies in a TLM-to-RTL design flow
Proceedings of the 44th annual Design Automation Conference
Race analysis for SystemC using model checking
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Race analysis for systemc using model checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Concurrency-oriented verification and coverage of system-level designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Verification and coverage of message passing multicore applications
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Designer-in-the-loop recoding of ESL models using static parallel access conflict analysis
Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems
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Concurrent interaction of multi-processor systems result in errors which are difficult to find. Traditional simulation-based verification techniques remove the concurrency information by arbitrary schedulings. We present a novel simulation-based technique for SystemC that preserves and exploits concurrency information. Our approach is unique in that we can detect potential errors in an observed execution, even if the error does not actually occur in that execution. We identify synchronization constructs in SystemC and develop predictive techniques for temporal assertion verification and deadlock detection. Our automated potential deadlock detection algorithm works on SystemC programs with semaphores, locks, wait and notify synchronizations and has less overhead compared with assertion verification. We patched SystemC kernel to implement our solution and obtained favorable results on industrial designs.