Partial order reduction for scalable testing of systemC TLM designs
Proceedings of the 45th annual Design Automation Conference
Predictive runtime verification of multi-processor SoCs in SystemC
Proceedings of the 45th annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
A Schedulerless Semantics of TLM Models Written in SystemC Via Translation into LOTOS
FM '08 Proceedings of the 15th international symposium on Formal Methods
Race analysis for SystemC using model checking
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Contract-Based Coordination of Hardware Components for the Development of Embedded Software
COORDINATION '09 Proceedings of the 11th International Conference on Coordination Models and Languages
Full simulation coverage for SystemC transaction-level models of systems-on-a-chip
Formal Methods in System Design
Formal Analysis of Non-determinism in Verilog Cell Library Simulation Models
FMICS '09 Proceedings of the 14th International Workshop on Formal Methods for Industrial Critical Systems
Verification of an industrial systemC/TLM model using LOTOS and CADP
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Race analysis for systemc using model checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test coverage for loose timing annotations
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Boosting lazy abstraction for systemc with partial order reduction
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Concurrency-oriented verification and coverage of system-level designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic analysis of DMA races using model checking and k-induction
Formal Methods in System Design
Automatic aspectization of systemC
Proceedings of the 2012 workshop on Modularity in Systems Software
Automatic analysis of scratch-pad memory code for heterogeneous multicore processors
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Symbolic model checking on SystemC designs
Proceedings of the 49th Annual Design Automation Conference
Fast and accurate TLM simulations using temporal decoupling for FIFO-based communications
Proceedings of the Conference on Design, Automation and Test in Europe
Conquering the scheduling alternative explosion problem of SystemC symbolic simulation
Proceedings of the International Conference on Computer-Aided Design
Hi-index | 0.00 |
SystemC is becoming a de-facto standard for the early simulation of Systems-on-a-chip (SoCs). It is a parallel language with a scheduler. Testing a SoC written in SystemC implies that we execute it, for some well chosen data. We are bound to use a particular deterministic implementation of the scheduler, whose specification is non-deterministic. Consequently, we may fail to discover bugs that would have appeared using another valid implementation of the scheduler. Current methods for testings SoCs concentrate on the generation of the inputs, and do not address this problem at all. We assume that the selection of relevant data is already done, and we generate several schedulings allowed by the scheduler specification. We use dynamic partial-order reduction techniques to avoid the generation of two schedulings that have the same effect on the system's behavior. Exploring alternative schedulings during testing is a way of guaranteeing that the SoC description, and in particular the embedded software, is scheduler-independent, hence more robust. The technique extends to the exploration of other non-fully specified aspects of SoC descriptions, like timing.