IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Model checking for programming languages using VeriSoft
Proceedings of the 24th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Automatic predicate abstraction of C programs
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
System Design with SystemC
Automatic Extraction of Functional Parallelism from Ordinary Programs
IEEE Transactions on Parallel and Distributed Systems
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Dynamic partial-order reduction for model checking software
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Design for Verification of SystemC Transaction Level Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
LusSy: A Toolbox for the Analysis of Systems-on-a-Chip at the Transactional Level
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
SystemC transaction level models and RTL verification
Proceedings of the 43rd annual Design Automation Conference
Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Improvements for constraint solving in the systemc verification library
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Formal Verification of Simulation Traces Using Computation Slicing
IEEE Transactions on Computers
Formal techniques for SystemC verification
Proceedings of the 44th annual Design Automation Conference
Formal verification of SystemC by automatic hardware/software partitioning
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Dynamic Model Checking with Property Driven Pruning to Detect Race Conditions
ATVA '08 Proceedings of the 6th International Symposium on Automated Technology for Verification and Analysis
Race analysis for SystemC using model checking
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Shortening the verification cycle with synthesizable abstract models
Proceedings of the 46th Annual Design Automation Conference
Full simulation coverage for SystemC transaction-level models of systems-on-a-chip
Formal Methods in System Design
Formal Analysis of Non-determinism in Verilog Cell Library Simulation Models
FMICS '09 Proceedings of the 14th International Workshop on Formal Methods for Industrial Critical Systems
Verification of an industrial systemC/TLM model using LOTOS and CADP
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Race analysis for systemc using model checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Sysfier: Actor-based formal verification of SystemC
ACM Transactions on Embedded Computing Systems (TECS)
Boosting lazy abstraction for systemc with partial order reduction
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Verifying SystemC: a software model checking approach
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Concurrency-oriented verification and coverage of system-level designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An analytic evaluation of SystemC encodings in Promela
Proceedings of the 18th international SPIN conference on Model checking software
Facilitating the design of fault tolerance in transaction level systemc programs
ICDCN'12 Proceedings of the 13th international conference on Distributed Computing and Networking
Symbolic model checking on SystemC designs
Proceedings of the 49th Annual Design Automation Conference
Verifying SystemC using an intermediate verification language and symbolic simulation
Proceedings of the 50th Annual Design Automation Conference
Facilitating the design of fault tolerance in transaction level SystemC programs
Theoretical Computer Science
Conquering the scheduling alternative explosion problem of SystemC symbolic simulation
Proceedings of the International Conference on Computer-Aided Design
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A SystemC simulation kernel consists of a deterministic implementation of the scheduler, whose specification is non-deterministic. To leverage testing of a SystemC TLM design, we focus on automatically exploring all possible behaviors of the design for a given data input. We combine static and dynamic partial order reduction techniques with SystemC semantics to intelligently explore a subset of the possible traces, while still being provably sufficient for detecting deadlocks and safety property violations. We have implemented our exploration algorithm in a framework called Satya and have applied it to a variety of examples including the TAC benchmark. Using Satya, we automatically found an assertion violation in a benchmark distributed as a part of the OSCI repository.