IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Bandera: extracting finite-state models from Java source code
Proceedings of the 22nd international conference on Software engineering
Slicing Software for Model Construction
Higher-Order and Symbolic Computation
SystemC: a homogenous environment to test embedded systems
Proceedings of the ninth international symposium on Hardware/software codesign
Automatic predicate abstraction of C programs
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Bebop: A Symbolic Model Checker for Boolean Programs
Proceedings of the 7th International SPIN Workshop on SPIN Model Checking and Software Verification
Fault Models and Test Generation for Hardware-Software Covalidation
IEEE Design & Test
Automatic synthesis of fault-tolerance
Automatic synthesis of fault-tolerance
Exploiting Symbolic Techniques in Automated Synthesis of Distributed Programs with Large State Space
ICDCS '07 Proceedings of the 27th International Conference on Distributed Computing Systems
Fault Injection Techniques and their Accelerated Simulation in SystemC
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Partial order reduction for scalable testing of systemC TLM designs
Proceedings of the 45th annual Design Automation Conference
SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
Multi-level fault modeling for transaction-level specifications
Proceedings of the 19th ACM Great Lakes symposium on VLSI
On the Use of Dynamic Binary Instrumentation to Perform Faults Injection in Transaction Level Models
DEPCOS-RELCOMEX '09 Proceedings of the 2009 Fourth International Conference on Dependability of Computer Systems
Race analysis for systemc using model checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A systemC/TLM semantics in PROMELA and its possible applications
Proceedings of the 14th international SPIN conference on Model checking software
Mutation Operators for Concurrent SystemC Designs
MTV '09 Proceedings of the 2009 10th International Workshop on Microprocessor Test and Verification
Codesign and Simulated Fault Injection of Safety-Critical Embedded Systems Using SystemC
EDCC '10 Proceedings of the 2010 European Dependable Computing Conference
PinaVM: a systemC front-end based on an executable intermediate representation
EMSOFT '10 Proceedings of the tenth ACM international conference on Embedded software
KRATOS: a software model checker for SystemC
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
An analytic evaluation of SystemC encodings in Promela
Proceedings of the 18th international SPIN conference on Model checking software
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Due to their increasing complexity, today's SoC (System on Chip) systems are subject to a variety of faults (e.g., soft errors, component crash, etc.), thereby making fault tolerance a highly important property of such systems. However, designing fault tolerance is a complex task in part due to the large scale of integration of SoC systems and different levels of abstraction provided by modern system design languages such as SystemC. Most existing methods enable fault injection and impact analysis as a means for increasing design dependability. Nonetheless, such methods provide little support for designing fault tolerance. To facilitate the design of fault tolerance in SoC systems, this paper propose an approach where fault tolerance is designed at the level of inter-component communication protocols in SystemC Transaction Level (TL) models. The proposed method includes four main steps, namely model extraction, fault modeling, addition of fault tolerance and refinement of synthesized fault tolerance to SystemC code. We demonstrate the proposed approach using a simple SystemC transaction level program that is subject to communication faults. We also provide a roadmap for future research at the intersection of fault tolerance and hardware-software co-design.