Facilitating the design of fault tolerance in transaction level systemc programs
ICDCN'12 Proceedings of the 13th international conference on Distributed Computing and Networking
On the Reuse of TLM Mutation Analysis at RTL
Journal of Electronic Testing: Theory and Applications
Facilitating the design of fault tolerance in transaction level SystemC programs
Theoretical Computer Science
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Functional design verification is the task of establishing that a given design accurately implements the intended functional behavior. Today, design verification has grown to dominate the cost of electronic system design, however, designs continue to be released with latent bugs. System level modeling is commonly used for designing concurrent SoCs in the industry. SystemC is the most popular concurrent system level description language. Non-determinism and concurrency problems such as starvation, interference and deadlock make it harder to verify concurrent programs than sequential programs. We plan to use mutation testing for verification of SystemC designs. Mutation testing is a fault injection based verification technique and has successfully been used in software testing. In this paper, we propose a fault model by developing mutation operators for concurrent SystemC designs. We aim to reap benefits of mutation testing for SystemC.