A Fortran 77 interpreter for mutation analysis
SIGPLAN '87 Papers of the Symposium on Interpreters and interpretive techniques
An experimental determination of sufficient mutant operators
ACM Transactions on Software Engineering and Methodology (TOSEM)
An experimental evaluation of selective mutation
ICSE '93 Proceedings of the 15th international conference on Software Engineering
POPL '80 Proceedings of the 7th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
ISSRE '02 Proceedings of the 13th International Symposium on Software Reliability Engineering
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An Empirical Study on Testing and Fault Tolerance for Software Reliability Engineering
ISSRE '03 Proceedings of the 14th International Symposium on Software Reliability Engineering
MuJava: an automated class mutation system: Research Articles
Software Testing, Verification & Reliability
On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On the Use of Mutation Faults in Empirical Assessments of Test Case Prioritization Techniques
IEEE Transactions on Software Engineering
SQLMutation: A tool to generate mutants of SQL database queries
MUTATION '06 Proceedings of the Second Workshop on Mutation Analysis
Basic Operations for Generating Behavioral Mutants
MUTATION '06 Proceedings of the Second Workshop on Mutation Analysis
Mutation Operators for Concurrent Java (J2SE 5.0)
MUTATION '06 Proceedings of the Second Workshop on Mutation Analysis
Jumble Java Byte Code to Measure the Effectiveness of Unit Tests
TAICPART-MUTATION '07 Proceedings of the Testing: Academic and Industrial Conference Practice and Research Techniques - MUTATION
Testing Programs with the Aid of a Compiler
IEEE Transactions on Software Engineering
A mutation model for the SystemC TLM 2.0 communication interfaces
Proceedings of the conference on Design, automation and test in Europe
Benchmarking Testing Strategies with Tools from Mutation Analysis
ICSTW '08 Proceedings of the 2008 IEEE International Conference on Software Testing Verification and Validation Workshop
An Introduction to High-Level Synthesis
IEEE Design & Test
Mutation Operators for Concurrent SystemC Designs
MTV '09 Proceedings of the 2009 10th International Workshop on Microprocessor Test and Verification
On the Mutation Analysis of SystemC TLM-2.0 Standard
MTV '09 Proceedings of the 2009 10th International Workshop on Microprocessor Test and Verification
SCEMIT: a systemc error and mutation injection tool
Proceedings of the 47th Design Automation Conference
Functional qualification of TLM verification
Proceedings of the Conference on Design, Automation and Test in Europe
Mutation analysis for SystemC designs at TLM
LATW '11 Proceedings of the 2011 12th Latin American Test Workshop
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Mutation analysis has gained consensus during the last decades as being an efficient technique for measuring the quality of SW testbench. More recently, it has been efficiently applied for validating testbenches of embedded system models implemented in hardware description language (HDL) at different abstraction levels (i.e., RTL, TLM). This article analyzes how mutation analysis performed at TLM can be reused at RTL and, in particular, how such a reuse can help designers in (i) optimizing the time spent for simulation at RTL, and (ii) improving the RTL testbench quality. Two alternatives of TLM mutation analysis reuse are presented and investigated for proposing an efficient methodology of RTL mutation analysis. Through experimental results, the proposed methodology is compared to the standard RTL mutation analysis to confirm its efficiency in terms of both simulation time and reached mutation coverage.