Constraint-Based Automatic Test Data Generation
IEEE Transactions on Software Engineering
Online minimization of transition systems (extended abstract)
STOC '92 Proceedings of the twenty-fourth annual ACM symposium on Theory of computing
Proceedings of the 37th Annual Design Automation Conference
Mutation Operators for Specifications
ASE '00 Proceedings of the 15th IEEE international conference on Automated software engineering
ISSRE '02 Proceedings of the 13th International Symposium on Software Reliability Engineering
An Empirical Study on Testing and Fault Tolerance for Software Reliability Engineering
ISSRE '03 Proceedings of the 14th International Symposium on Software Reliability Engineering
A component-based specification approach for embedded systems using FDTs
SAVCBS '05 Proceedings of the 2005 conference on Specification and verification of component-based systems
On the Use of Mutation Faults in Empirical Assessments of Test Case Prioritization Techniques
IEEE Transactions on Software Engineering
ExMAn: A Generic and Customizable Framework for Experimental Mutation Analysis
MUTATION '06 Proceedings of the Second Workshop on Mutation Analysis
Mutation Operators for Concurrent Java (J2SE 5.0)
MUTATION '06 Proceedings of the Second Workshop on Mutation Analysis
Testing Software Design Modeled by Finite-State Machines
IEEE Transactions on Software Engineering
Multi-level fault modeling for transaction-level specifications
Proceedings of the 19th ACM Great Lakes symposium on VLSI
SCEMIT: a systemc error and mutation injection tool
Proceedings of the 47th Design Automation Conference
Functional qualification of TLM verification
Proceedings of the Conference on Design, Automation and Test in Europe
HIFsuite: tools for HDL code conversion and manipulation
EURASIP Journal on Embedded Systems
Concurrency-oriented verification and coverage of system-level designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A LEON3 virtual platform with real spacewire interfaces for dependable space software development
Proceedings of the 4th International ICST Conference on Simulation Tools and Techniques
Generation of TLM testbenches using mutation testing
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
On the Reuse of TLM Mutation Analysis at RTL
Journal of Electronic Testing: Theory and Applications
Verification coverage of embedded multicore applications
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Mutation analysis is a widely-adopted strategy in software testing with two main purposes: measuring the quality of test suites, and identifying redundant code in programs. Similar approaches are applied in hardware verification and testing too, especially at RTL or gate level, where mutants are generally referred as faults, and mutation analysis is performed by means of fault modeling and fault simulation. However, in modern embedded systems there is a close integration between HW and SW parts, and verification strategies should be applied early in the design flow. This requires the definition of new mutation analysis-based strategies that work at system level, where HW and SW functionalities are not partitioned yet. In this context, the paper proposes a mutation model for perturbing transaction level modeling (TLM) SystemC descriptions. In particular, the main constructs provided by the SystemC TLM 2.0 library have been analyzed, and a set of mutants is proposed to perturb the primitives related to the TLM communication interfaces.