Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 37th Annual Design Automation Conference
Fault Injection Techniques and Tools
Computer
Software-Implemented Fault Injection Methodology for Design and Validation of System Fault Tolerance
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Comparison and Application of Different VHDL-Based Fault Injection Techniques
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Verification of Transaction-Level SystemC models using RTL Testbenches
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Laerte++: an object oriented high-level TPG for systemC designs
Languages for system specification
SystemC-VHDL Co-Simulation and Synthesis in the HW Domain
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
A component-based specification approach for embedded systems using FDTs
SAVCBS '05 Proceedings of the 2005 conference on Specification and verification of component-based systems
FATE: a Functional ATPG to Traverse Unstabilized EFSMs
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Properties Incompleteness Evaluation by Functional Verification
IEEE Transactions on Computers
Towards Equivalence Checking Between TLM and RTL Models
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
Integrating RTL IPs into TLM designs through automatic transactor generation
Proceedings of the conference on Design, automation and test in Europe
A mutation model for the SystemC TLM 2.0 communication interfaces
Proceedings of the conference on Design, automation and test in Europe
Logic-level mapping of high-level faults
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Specification, Synthesis, and Simulation of Transactor Processes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Time-Constraint-Aware Optimization of Assertions in Embedded Software
Journal of Electronic Testing: Theory and Applications
On the Reuse of Heterogeneous IPs into SysML Models for Integration Validation
Journal of Electronic Testing: Theory and Applications
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HIFSuite ia a set of tools and application programming interfaces (APIs) that provide support for modeling and verification of HW/SW systems. The core of HIFSuite is the HDL Intermediate Format (HIF) language upon which a set of front-end and back-end tools have been developed to allow the conversion of HDL code into HIF code and vice versa. HIFSuite allows designers to manipulate and integrate heterogeneous components implemented by using different hardware description languages (HDLs). Moreover, HIFSuite includes tools, which rely on HIF APIs, for manipulating HIF descriptions in order to support code abstraction/refinement and postrefinement verification.