A systematic IP and bus subsystem modeling for platform-based system design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Incremental ABV for functional validation of TL-to-RTL design refinement
Proceedings of the conference on Design, automation and test in Europe
System on Chips optimization using ABV and automatic generation of SystemC codes
Microprocessors & Microsystems
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Graph based test case generation for TLM functional verification
Microprocessors & Microsystems
Integrating RTL IPs into TLM designs through automatic transactor generation
Proceedings of the conference on Design, automation and test in Europe
HIFsuite: tools for HDL code conversion and manipulation
EURASIP Journal on Embedded Systems
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Hardware design and simulation for verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Automatic RTL Test Generation from SystemC TLM Specifications
ACM Transactions on Embedded Computing Systems (TECS)
SystemC simulation on GP-GPUs: CUDA vs. OpenCL
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators
International Journal of Parallel Programming
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System architects working on SoC design havetraditionally been hampered by the lack of a coherentemethodology for architecture evaluation and coverificationof hardware and software. SystemC 2.0facilitates the development of Transaction-Level Models(TLMs) which are models of the hardware systemcomponents at higher level of abstraction than RTL. Dueto lower modeling effort yet higher simulation speed,TLMs are useful for architectural exploration,algorithmic evaluation, hardware-software partitioningand software development. The problems posed by SOCdesign methodologies require development of models athigher abstraction also for the earlier developed IP's.The development time of a TLM IP is already low, so if wecan reduce the verification time by re-use of the earlierRTL test benches we can reduce the overall cost of suchan IP TLM. This paper focusses on the methodology touse the RTL testbenches for verification of a SystemCmodel of the same IP at a higher abstraction level(Transaction level) , some tools available in the marketto support this testbench reuse and the implementationchallenges posed by the mentioned verificationtechnique.