Verification of Transaction-Level SystemC models using RTL Testbenches
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Efficient assertion based verification using TLM
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Functional Test-Case Generation by a Control Transaction Graph for TLM Verification
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
A systematic approach to configurable functional verification of HW IP blocks at transaction level
Computers and Electrical Engineering
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Describing complex systems at a high level of abstraction provides designers with the possibility of exploring multiple SoC design architectures before committing to the low level-details of a complete implementation. Transaction level modeling understandably expedites the design simulation and verification. During the verification process, generating good test cases plays a significant role in determining the quality of the design. Inadequate test cases may cause bugs to remain. In this paper, first, in order to generate test cases for a TL model, we present a Control-Transaction Graph (CTG) which describes the behavior of a TL Model. A Control Graph is a control flow graph of a module in the design and transactions represent the interactions such as synchronization between modules. Second, we define dependent paths (DePaths) on the CTG as test cases for a transaction level model, which can find communication errors in simulation. We also give coverage metrics for a TL model to measure the quality of the generated test cases. Finally, we apply our method on the SystemC model of AMBA-AHB bus and JPEG encoder and generate test cases based on the CTG of these models.