Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An automatic testbench generation tool for a SystemC functional verification methodology
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
SystemC transaction level models and RTL verification
Proceedings of the 43rd annual Design Automation Conference
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
An assertion-based verification methodology for system-level design
Computers and Electrical Engineering
Hybrid, Incremental Assertion-Based Verification for TLM Design Flows
IEEE Design & Test
System on Chips optimization using ABV and automatic generation of SystemC codes
Microprocessors & Microsystems
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Graph based test case generation for TLM functional verification
Microprocessors & Microsystems
Design and verification of systemc transaction-level models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With demand growing by the day, the complexity of electronic devices is constantly increasing. Since simulation is still the most used approach, functional verification has become one of the major bottlenecks in the design and verification flow. In this paper we propose a systematic approach to configurable functional verification of electronic devices. Based on a black box approach, it can be applied to any design where behavior can be expressed by a set of functions. It combines simulation- and assertion-based verification into a hybrid verification. The proposed specification-based coverage metric can be configured ranging from a very rapid to an exhaustive verification. The approach uses Transaction Level (TL) modeling to raise the abstraction level, providing faster verification. The results of the proposed design and verification flow, Intellectual Property (IP) and Test Bench (TB) are reusable. The approach is demonstrated on two case-studies; a video-processing IP block and universal serial bus host controller. The results consider both simulation times and TB generation times.