Decision procedures and expressiveness in the temporal logic of branching time
Journal of Computer and System Sciences
On behavior fault modeling for digital designs
Journal of Electronic Testing: Theory and Applications
Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Symbolic functional vector generation for VHDL specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Symbolic Model Checking
Art of Software Testing
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Dos and don'ts of CTL state coverage estimation
Proceedings of the 40th annual Design Automation Conference
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
ETW '00 Proceedings of the IEEE European Test Workshop
On the Use of a High-Level Fault Model to Check Properties Incompleteness
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Verification of Transaction-Level SystemC models using RTL Testbenches
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Assertion-Based Design
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Defining coverage views to improve functional coverage analysis
Proceedings of the 41st annual Design Automation Conference
Systematic functional coverage metric synthesis from hierarchical temporal event relation graph
Proceedings of the 41st annual Design Automation Conference
Coverage of Formal Properties Based on a High-Level Fault Model and Functional ATPG
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Transition-based coverage estimation for symbolic model checking
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
FSM-based transaction-level functional coverage for interface compliance verification
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling
MTV '05 Proceedings of the Sixth International Workshop on Microprocessor Test and Verification
A systematic approach to configurable functional verification of HW IP blocks at transaction level
Computers and Electrical Engineering
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In transaction-level modeling (TLM), verification methodologies based on transactions allow testbenches, properties, and IP cores in mixed TL-RTL designs to be reused. However, no papers in the literature analyze the effectiveness of transaction-based verification (TBV) in comparison to the more traditional RTL approach. The first contribution of this article is the introduction of a functional-fault-model-based methodology for demonstrating the effectiveness of reuse through TBV. A second contribution is the introduction of a similar methodology for efficient property checking which identifies and removes redundant properties prior to assertion-based verification or model checking.