An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Functional Verification of Networked Embedded Systems
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Transition-based coverage estimation for symbolic model checking
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
BUSpec: A framework for generation of verification aids for standard bus protocol specifications
Integration, the VLSI Journal
Too Few or Too Many Properties? Measure it by ATPG!
Journal of Electronic Testing: Theory and Applications
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A theory of mutations with applications to vacuity, coverage, and fault tolerance
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
| Hi-index | 0.00 |
The use of model checking to validate descriptions ofdigital systems lacks a coverage metrics. The set of provenproperties can be incomplete, thus not guaranteeing the behavioralchecking completeness of the digital system implementationwith respect to the specification. This paper proposesa coverage methodology based on a combination ofmodel checking, high-level fault simulation and automatictest pattern generation, to estimate the incompleteness of aset of formal properties. The adopted high-level fault modelallows to join dynamic and formal verification.