Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Toward formalizing a validation methodology using simulation coverage
DAC '97 Proceedings of the 34th annual Design Automation Conference
Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Dos and don'ts of CTL state coverage estimation
Proceedings of the 40th annual Design Automation Conference
On the Use of a High-Level Fault Model to Check Properties Incompleteness
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Formal verification coverage: computing the coverage gap between temporal specifications
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Extended abstract: transition traversal coverage estimation for symbolic model checking
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Properties Incompleteness Evaluation by Functional Verification
IEEE Transactions on Computers
Too Few or Too Many Properties? Measure it by ATPG!
Journal of Electronic Testing: Theory and Applications
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The role of mutation analysis for property qualification
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
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Lack of complete formal specification is one of the major obstacles for the deployment of model checking. Coverage estimation addresses this issue by revealing the unverified part of the design according to the specified properties. In this paper we propose a new transition-based coverage metric to evaluate the completeness of properties for symbolic model checking. It is more comprehensive and accurate than the existing coverage metrics for model checking. An efficient symbolic algorithm is presented for computing the transition coverage for a subset of ACTL. Our coverage estimator has been applied to the model checking of a cache coherence protocol. We uncovered several coverage holes including one that eventually led to the discovery of a design bug.