Decision procedures and expressiveness in the temporal logic of branching time
Journal of Computer and System Sciences
Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Symbolic functional vector generation for VHDL specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Symbolic Model Checking
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Coverage Metrics for Temporal Logic Model Checking
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Dos and don'ts of CTL state coverage estimation
Proceedings of the 40th annual Design Automation Conference
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
ETW '00 Proceedings of the IEEE European Test Workshop
On the Use of a High-Level Fault Model to Check Properties Incompleteness
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Fault Models and Test Generation for Hardware-Software Covalidation
IEEE Design & Test
Laerte++: an object oriented high-level TPG for systemC designs
Languages for system specification
Transition-based coverage estimation for symbolic model checking
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
FATE: a Functional ATPG to Traverse Unstabilized EFSMs
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Extended abstract: transition traversal coverage estimation for symbolic model checking
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Concurrency-oriented verification and coverage of system-level designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Verification of a design, based on model checking, requires the identification of a set of formal properties manually derived from the specification of the design under verification (DUV). Such a set can include too few or too many properties. This paper proposes to use a functional ATPG to identify missing properties and to remove unnecessary ones. In particular, the paper refines, extends, and compares, with other symbolic approaches, a methodology to estimate the completeness of formal properties, which exploits a functional fault model and a functional ATPG. Moreover, the same fault model and ATPG are used to face the opposite problem of identifying useless properties, that is, properties which are in logical consequence. Logical consequence between properties is generally examined by using theorem proving, which may require a large amount of time and space resources. On the contrary, the paper proposes a faster approach which analyzes logical consequence by observing the property capability of revealing functional faults. The joint use of the methodologies allows to optimize the set of properties used for several verification sessions needed to check all design phases of an incremental design flow.