On behavior fault modeling for digital designs
Journal of Electronic Testing: Theory and Applications
Computing binary decision diagrams for VHDL data types
EURO-DAC '94 Proceedings of the conference on European design automation
Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Generation of BDDs from hardware algorithm descriptions
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
User defined coverage—a tool supported methodology for design verification
DAC '98 Proceedings of the 35th annual Design Automation Conference
Functional vector generation for HDL models using linear programming and 3-satisfiability
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Constraint Slving for Test Case Generation
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Automatic VHDL Restructuring for RTL Synthesis Optimization and Testability Improvement
ICCD '98 Proceedings of the International Conference on Computer Design
Virtual fault simulation of distributed IP-based designs
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Functional test generation for behaviorally sequential models
Proceedings of the conference on Design, automation and test in Europe
SystemC: a homogenous environment to test embedded systems
Proceedings of the ninth international symposium on Hardware/software codesign
An error simulation based approach to measure error coverage of formal properties
Proceedings of the 12th ACM Great Lakes symposium on VLSI
ARPIA: A High-Level Evolutionary Test Signal Generator
Proceedings of the EvoWorkshops on Applications of Evolutionary Computing
Mixing ATPG and property checking for testing HW/SW interfaces
Proceedings of the 13th ACM Great Lakes symposium on VLSI
An Application of Genetic Algorithms and BDDs to Functional Testing
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
An EFSM-based approach for functional ATPG
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Redundant functional faults reduction by saboteurs synthesis [logic verification]
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
EFSM Manipulation to Increase High-Level ATPG Effectiveness
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Properties Incompleteness Evaluation by Functional Verification
IEEE Transactions on Computers
Too Few or Too Many Properties? Measure it by ATPG!
Journal of Electronic Testing: Theory and Applications
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic RTL Test Generation from SystemC TLM Specifications
ACM Transactions on Embedded Computing Systems (TECS)
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