On behavior fault modeling for digital designs
Journal of Electronic Testing: Theory and Applications
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Combining deterministic and genetic approaches for sequential circuit test generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Symbolic functional vector generation for VHDL specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testability Analysis and ATPG on Behavioral RT-Level VHDL
Proceedings of the IEEE International Test Conference
Alternating Strategies for Sequential Circuit ATPG
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Testability Alternatives Exploration through Functional Testing
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A genetic algorithm framework for test generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SystemC: a homogenous environment to test embedded systems
Proceedings of the ninth international symposium on Hardware/software codesign
Assertion-based automated functional vectors generation using constraint logic programming
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A framework for the functional verification of systemC models
International Journal of Parallel Programming
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The paper describes a functional level test pattern generator, which combines two techniques: genetic algorithms (GAs) and binary decision diagrams (BDDs). The combined execution of such two techniques achieves better results for functional testing, than the single application of each separated technique. The entire set of functional errors is examined in a shorter time and a more compact test set is produced. The reason of this interesting result has been analyzed in the paper. It meanly depends on the fact that hard to detect errors for GA-based testing techniques are easy to detect errors for BDD-based techniques and vice versa. The two testing approaches are thus complementary and can effectively cooperate.