IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Symbolic functional vector generation for VHDL specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Art of Software Testing
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
ETW '00 Proceedings of the IEEE European Test Workshop
An Application of Genetic Algorithms and BDDs to Functional Testing
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A genetic algorithm framework for test generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
AMLETO: A Multi-language Environment for Functional Test Generation
ITC '01 Proceedings of the 2001 IEEE International Test Conference
SystemC
Fault Models and Test Generation for Hardware-Software Covalidation
IEEE Design & Test
Hardware/software partitioning of software binaries: a case study of H.264 decode
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A system for automatic testing of embedded software in undergraduate study exercises
ACM SIGBED Review - Special issue: The first workshop on embedded system education (WESE)
A code refinement methodology for performance-improved synthesis from C
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Thread warping: a framework for dynamic synthesis of thread accelerators
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
C is for circuits: capturing FPGA circuits as sequential code for portability
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Facilitating the design of fault tolerance in transaction level systemc programs
ICDCN'12 Proceedings of the 13th international conference on Distributed Computing and Networking
The RACECAR heuristic for automatic function specialization on multi-core heterogeneous systems
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Facilitating the design of fault tolerance in transaction level SystemC programs
Theoretical Computer Science
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The SystemC language is becoming a new standard in the EDA field and many designers are starting to use it to model complex systems. SystemC has been mainly adopted to define abstract models of hardware/software components, since they can be easily integrated for rapid prototyping. However, it can also be used to describe modules at a higher level of detail, e.g., RT-level hardware descriptions and assembly software modules. Thus, it would be possible to imagine a SystemC-based design flow, where the system description is translated from one abstraction level to the following one by always using SystemC representations. The adoption of a SystemC-based design flow would be particularly efficient for testing purpose as shown in this paper. In fact, it allows the definition of a homogeneous testing procedure, applicable to all design phases, based on the same error model and on the same test generation strategy. Moreover, test patterns are indifferently applied to hardware and software components, thus making the proposed testing methodology particularly suitable for embedded systems. Test patterns are generated on the SystemC description modeling the system at one abstraction level, then, they are used to validate the translation of the system to a lower abstraction level. New test patterns are then generated for the lower abstraction level to improve the quality of the test set and this process is iterated for each translation (synthesis) step.