Software testing techniques (2nd ed.)
Software testing techniques (2nd ed.)
PIE: A Dynamic Failure-Based Technique
IEEE Transactions on Software Engineering
Dynamic impact analysis: a cost-effective technique to enforce error-propagation
ISSTA '93 Proceedings of the 1993 ACM SIGSOFT international symposium on Software testing and analysis
Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
DAC '96 Proceedings of the 33rd annual Design Automation Conference
The automatic generation of functional test vectors for Rambus designs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An observability-based code coverage metric for functional simulation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Toward formalizing a validation methodology using simulation coverage
DAC '97 Proceedings of the 34th annual Design Automation Conference
The Verilog hardware description language (4th ed.)
The Verilog hardware description language (4th ed.)
Logical Design of Digital Systems
Logical Design of Digital Systems
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Coverage-Directed Test Generation Using Symbolic Techniques
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Symbolic functional vector generation for VHDL specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Verification Simulation Acceleration UsingCode-Perturbation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Automatic test bench generation for validation of RT-level descriptions: an industrial experience
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Functional test generation for behaviorally sequential models
Proceedings of the conference on Design, automation and test in Europe
SystemC: a homogenous environment to test embedded systems
Proceedings of the ninth international symposium on Hardware/software codesign
Observability analysis of embedded software for coverage-directed validation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
Journal of Electronic Testing: Theory and Applications
Fast Anti-Random (FAR) Test Generation to Improve the Quality of Behavioral Model Verification
Journal of Electronic Testing: Theory and Applications
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Automatic Validation of Protocol Interfaces Described in VHDL
Real-World Applications of Evolutionary Computing, EvoWorkshops 2000: EvoIASP, EvoSCONDI, EvoTel, EvoSTIM, EvoROB, and EvoFlight
ARPIA: A High-Level Evolutionary Test Signal Generator
Proceedings of the EvoWorkshops on Applications of Evolutionary Computing
Coverage Metrics for Temporal Logic Model Checking
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
A Practical Approach to Coverage in Model Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Implicit Functionality and Multiple Branch Coverage (IFMB): a Testability Metric for RT-Level
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Fault Models and Test Generation for Hardware-Software Covalidation
IEEE Design & Test
A Probabilistic Method for the Computation of Testability of RTL Constructs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
FSM-based transaction-level functional coverage for interface compliance verification
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Event-driven observability enhanced coverage analysis of C programs for functional validation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An efficient control-oriented coverage metric
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A coverage metric for the validation of interacting processes
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Coverage metrics for temporal logic model checking
Formal Methods in System Design
Clock domain crossing fault model and coverage metric for validation of SoC design
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 20th annual conference on Integrated circuits and systems design
A new testability guided abstraction to solving bit-vector formula
SMT '08/BPR '08 Proceedings of the Joint Workshops of the 6th International Workshop on Satisfiability Modulo Theories and 1st International Workshop on Bit-Precise Reasoning
Applied Assertion-Based Verification: An Industry Perspective
Foundations and Trends in Electronic Design Automation
SCEMIT: a systemc error and mutation injection tool
Proceedings of the 47th Design Automation Conference
A novel mutation-based validation paradigm for high-level hardware descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Concurrency-oriented verification and coverage of system-level designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Electronic Testing: Theory and Applications
Coverage-directed observability-based validation for embedded software
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Functional simulation is still the primary workhorse for verifying the functional correctness of hardware designs. Functional verification is necessarily incomplete because it is not computationally feasible to exhaustively simulate designs. It is important therefore to quantitatively measure the degree of verification coverage of the design. Coverage metrics proposed for measuring the extent of design verification provided by a set of functional simulation vectors should compute statement execution counts (controllability information), and check to see whether effects of possible errors activated by program stimuli can be observed at the circuit outputs (observability information). Unfortunately, the metrics proposed thus far, either to not compute both types of information, or are inefficient, i.e., the overhead of computing the metric is very large.In this paper, we provide the details of an efficient method to compute an Observability-based Code COverage Metric (OCCOM) that can be used while simulating complex HDL designs. This method offers a more accurate assessment of design verification coverage than line coverage, and is significantly more computationally efficient than prior efforts to assess observability information because it breaks up the computation into two phases: Functional simulation of a modified HDL model, followed by analysis of a flowgraph extracted from the HDL model. Commercial HDL simulators can be directly used for the time-consuming first phase, and the second phase can be performed efficiently using concurrent evaluation techniques.