Behavioral fault simulation in VHDL
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
Software Testing Techniques
Using Target Faults To Detect Non-Tartget Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
From Specification Validation to Hardware Testing: A Unified Method
Proceedings of the IEEE International Test Conference on Test and Design Validity
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
ETW '00 Proceedings of the IEEE European Test Workshop
Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Behavioral Fault Modeling in a VHDL Synthesis Environment
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
REGISTER-TRANSFER LEVEL FAULT MODELING AND TEST EVALUATION TECHNIQUES FOR VLSI CIRCUITS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
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The purpose of this paper is to introduce a new RTLtestability metric, IFMB, that evaluates the exercise ofImplicit Functionality (IF) of operators and MultipleBranch (MB) coverage of conditional constructs.Although physical Defect Coverage (DC) stronglydepends on the logic structure, thus preventing accurateDC estimation, RTL fault models can be derived,targeting high correlation between RTL fault coverageand DC.Using this evaluation criterion, previous RTLcoverage metrics are compared with new metric.Due toits excellent correlation to DC, IFMB allows, at RT-level,test pattern quality evaluation aiming its reuse asproduction or lifetime test, using BIST.A methodology fortestability analysis with the proposed RTL fault models isalso presented, based on fast fault simulation using random patterns.Simulation based testability analysiserrors are quantified.Examples are presented where theproposed testability metrics are used to guide theinclusion of BIST in modules of ITC'99 benchmarkcircuits.