An integrated approach to software engineering
An integrated approach to software engineering
Performance and fault modeling with VHDL
Performance and fault modeling with VHDL
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A design for testability technique for RTL circuits using control/data flow extraction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Behavioral-Level Fault Simulation
IEEE Design & Test
Hierarchical Functional-Fault Simulation for High-Level Synthesis
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Proceedings of the IEEE International Test Conference on Test and Design Validity
Improving Gate Level Fault Coverage by RTL Fault Grading
Proceedings of the IEEE International Test Conference on Test and Design Validity
Design for Testability Using Architectural Descriptions
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Practical code coverage for Verilog
IVC '95 Proceedings of the 4th IEEE International Verilog HDL Conference
B-algorithm: a behavioral test generation algorithm
ITC'94 Proceedings of the 1994 international conference on Test
On behavior fault modeling for combinational digital designs
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Automatic test bench generation for simulation-based validation
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Automatic test bench generation for validation of RT-level descriptions: an industrial experience
DATE '00 Proceedings of the conference on Design, automation and test in Europe
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
Journal of Electronic Testing: Theory and Applications
Fast Anti-Random (FAR) Test Generation to Improve the Quality of Behavioral Model Verification
Journal of Electronic Testing: Theory and Applications
Behavioral-Level DFT via Formal Operator Testability Measures
Journal of Electronic Testing: Theory and Applications
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
Automatic Validation of Protocol Interfaces Described in VHDL
Real-World Applications of Evolutionary Computing, EvoWorkshops 2000: EvoIASP, EvoSCONDI, EvoTel, EvoSTIM, EvoROB, and EvoFlight
On automatic generation of RTL validation test benches using circuit testing techniques
Proceedings of the 13th ACM Great Lakes symposium on VLSI
System-Level Test Bench Generation in a Co-Design Framework
ETW '00 Proceedings of the IEEE European Test Workshop
REGISTER-TRANSFER LEVEL FAULT MODELING AND TEST EVALUATION TECHNIQUES FOR VLSI CIRCUITS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Implicit Functionality and Multiple Branch Coverage (IFMB): a Testability Metric for RT-Level
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Fault Models and Test Generation for Hardware-Software Covalidation
IEEE Design & Test
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level
Journal of Electronic Testing: Theory and Applications
FSM-based transaction-level functional coverage for interface compliance verification
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A coverage metric for the validation of interacting processes
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Holistic verification: myth or magic bullet?
Proceedings of the 46th Annual Design Automation Conference
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences
Journal of Electronic Testing: Theory and Applications
Using model-based test program generator for simulation validation
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
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Current code coverage metrics used in high level VLSI design methodology are based on statement, branch, toggle and condition coverages of the HDL code obtained by simulating validation vectors. These measures allow the designer to find sections of the HDL code not executed during validation. Feedback from the code coverage analysis helps generate additional vectors to exercise previously unexercised functionality. In this paper, we explore the relationship between results of RTL code coverage and the gate level fault coverage. Based on the observations of this empirical study we propose a new and improved code coverage metric ``Validation Vector Grade(VVG).'' The VVG-approach modifies code coverage metrics by adding the concepts of observability and arithmetic fault library. VVG is an improved validation metric, which can also be used for early testability analysis at the RT level. Results of the VVG-approach at RT level are shown to be good indicators of the structural fault coverage. Experiments on actual telecommunication VLSI chip designs show that the VVG reported at the RT level can predict the post-synthesis gate level fault coverage with an error margin less than 4%. Also, the improvements in VVG at the RT level due to high-level design changes or added vectors track improvements in gate level fault coverage.